A clocked electronic circuit (for example, a microprocessor) often radiates electromagnetic energy at the frequency of a clock signal that clocks the electronic circuit. The electronic circuit also typically radiates electromagnetic energy at the frequencies of harmonics of the frequency of the clock signal. Power leads and long traces on a printed circuit board can act as antennas to radiate electromagnetic energy. Such electromagnetic energy emitted by one electronic device can be received by another electronic device and can interfere with the operation of the other electronic device. The radiated electromagnetic energy is therefore sometimes called electromagnetic interference (EMI). Thus, the Federal Communications Commission regulates the maximum allowable emission of EMI by electronic consumer devices.
Manufacturers of electronic devices use various methods to reduce emission of EMI. One method involves shielding the electronic circuits that emit the EMI. Shielding circuits with a metal casing, however, can be costly. Moreover, EMI can escape through openings in a metal shield. Another method of reducing EMI involves reducing the length of signal paths that carry clock signals. It is often not feasible, however, significantly to reduce the length of all signal paths that carry clock signals. Finally, the undesirable effects of EMI can be reduced by spreading out the frequency bandwidth of a clock signal in order to decrease the peak emission level of EMI. Spreading out the frequency bandwidth of a clock signal is sometimes referred to as “spread spectrum clocking.” For example, spread spectrum clocking can be used to reduce the peak EMI levels emitted from an electronic consumer device so that the EMI levels are within maximum levels permitted by the Federal Communications Commission.
One existing method for spread spectrum clocking is described in U.S. Pat. No. 5,488,627, in which a spread spectrum output clock is generated by a spread spectrum clock generator that includes a phase locked loop (PLL). One problem with PLL spread spectrum clock generators is that they typically include loop filter capacitors. Loop filter capacitors are typically large and costly to realize in integrated circuit form.
Another problem with PLL spread spectrum clock generators is the resulting reduction in processing throughput of the microprocessor that is clocked by the spread spectrum clock signal. Microprocessors typically have maximum allowable clock frequencies. A microprocessor may fail if the clock signal is increased beyond the maximum frequency. For many applications, it is desired to operate the microprocessor with the highest frequency clock signal possible in order to maximize microprocessor processing throughput. In order to perform the spread spectrum clock generation, however, the frequency of the clock signal is dithered between the maximum frequency and a lesser frequency. The average clock frequency is therefore lower than the maximum clock frequency. The result is an undesired reduction in microprocessor throughput.
Due to the interest in maximizing processing throughput, spread spectrum clocking of a microprocessor may be practiced by varying the frequency of the clock signal just enough to bring the peak EMI levels within the maximum permitted levels, while at the same time maintaining the fastest possible average clock frequency. Consequently, it is desirable to control the variations in the frequency of the spread spectrum clock.
One existing method for controlling the variations in the frequency of a spread spectrum clock signal involves switching between a plurality of delayed clock signals. FIG. 1 (prior art) shows a spread spectrum system 10 as described in U.S. Pat. No. 6,643,317. Spread spectrum clock system 10 includes a clock signal generator 11, a state machine 12 and a multiplexer 13. Clock signal generator 11 outputs a primary clock signal 14, and multiplexer 13 outputs a spread spectrum signal 15. The output of clock signal generator 11 is coupled to state machine 12 and to a data input lead of multiplexer 13, as well as to delay lines 16-18 through delay line N 19. The output of state machine 12 is coupled to a select input lead of multiplexer 13. Each of delay lines 16-18 through delay line N 19 outputs a signal that is delayed to a different degree. The outputs of delay lines 16-19 are coupled to data input leads of multiplexer 13. Based on primary clock signal 14, state machine 12 generates a select signal 20 that causes multiplexer 13 to switch between primary clock signal 14 and the delayed signals from delay lines 16-19. In this manner, spread spectrum signal 15 is generated from signals that are delayed by discrete amounts. For additional information, see U.S. Pat. No. 6,643,317.
Generating a spread spectrum clock signal by switching between signals having different, discrete frequencies can produce unwanted frequency components in the spread spectrum clock signal. A method is sought for generating a spread spectrum clock signal that does not involve a phase locked loop and that does not rely on discrete delayed signals.